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Additional resources for Advanced Xilinx Fpga Design With Ise
Review Questions • • • What is the main difference between the LogiCORE and the AllianceCORE products? exe? What is the difference between the VHO/VEO files and the VHD/V files that are created by the CORE Generator™ system? CORE Generator System - 9 - 26 © 2003 Xilinx, Inc. All Rights Reserved Answers • What is the main difference between the LogiCORE and the AllianceCORE products? exe? – • LogiCORE products are sold and supported by Xilinx AllianceCORE products are sold and supported by AllianceCORE partners Makes it easy to compile the XilinxCoreLib library before your first behavioral simulation What is the difference between the VHO/VEO files and the VHD/V files that are created by the CORE Generator™ system?
All Rights Reserved I/O Timing: Solutions • • Use a DCM to remove clock distribution delay Register all top-level inputs and outputs – • IOB flip-flops have the best timing Increase the slew rate or drive strength on outputs – Only available for LVCMOS and LVTTL I/O standards Timing Closure with Timing Analyzer - 23 © 2003 Xilinx, Inc. All Rights Reserved Outline • • • • Timing Closure with Timing Analyzer - 24 Timing Reports Interpreting Timing Reports Report Options Summary © 2003 Xilinx, Inc.
All Rights Reserved Timing Analyzer GUI • Hierarchical browser – • Current position in the report – • Quickly navigate to specific report sections Identifies the portion of the report that is displayed in the text window Report text – Links to the Timing Improvement Wizard, Interactive Data Sheet and Floorplanner, highlighted in blue Timing Closure with Timing Analyzer - 8 © 2003 Xilinx, Inc. All Rights Reserved Cross Probing • • • Shows the placement of logic in a delay path To enable cross probing, use the command: View → Floorplanner for Cross probing Click highlighted text – The corresponding logic is selected in the Floorplanner Timing Closure with Timing Analyzer - 9 © 2003 Xilinx, Inc.